Quest Global
Solving the world’s hardest engineering challenges through end‑to‑end solutions across industries.
Physical Verification Engineer
Perform chip-level physical verification, IR/EM analysis, and automation scripting.
Job Highlights
About the Role
• Set up, analyze, and sign off full chip and block-level physical design verification (PDV) runs. • Apply deep knowledge of PDV checks such as LVS, DRC, ERC, soft checks, PERC, and DFM. • Debug and resolve PDV issues including DRC, LVS, ERC, and LU-ESD, using Calibre. • Perform full chip IR drop and electromigration (EM) analysis with vector and vectorless methods, including package SIP (BGA/FC) and DFT shift/capture vectors. • Run and troubleshoot IR‑EM analyses, leveraging Redhawk‑SC tools. • Develop and support automated scripts and flows for IR‑EM and PDV.
Key Responsibilities
- ▸pdv runs
- ▸lvs checks
- ▸drc checks
- ▸ir‑em analysis
- ▸redhawk‑sc
- ▸automation scripts
What You Bring
• Demonstrate 2–10 years of experience in chip/partition level PDV and IR‑EM with minimal supervision.
Requirements
- ▸2-10 years
- ▸pdv
- ▸ir-em
- ▸chip level
- ▸partition level
- ▸minimal supervision
Work Environment
Onsite