Quest Global
Solving the world’s hardest engineering challenges through end‑to‑end solutions across industries.
Senior Physical Design Engineer
Senior Physical Design Engineer handling low‑node (≤4nm) PD, tape‑out and sign‑off tasks.
Job Highlights
About the Role
The role focuses on advanced semiconductor design, requiring collaboration across multiple teams to deliver high‑quality tape‑out sign‑offs and maintain robust design integrity. • Perform pre‑DRC/DRC reviews and manual physical verification fixes. • Debug logs, reports, and timing issues; apply timing fixes and ECOs.
Key Responsibilities
- ▸drc review
- ▸physical verification
- ▸debugging
- ▸timing fixes
- ▸ecos
- ▸tape-out
What You Bring
• Experience with lower‑tech nodes (4nm and below) and basic synthesis knowledge. • Strong floorplanning, sanity checks, and CTS‑HTS expertise. • EM/IR analysis expertise. • 2‑3 tape‑out experiences from netlist to GDS sign‑off. • Ability to multitask and run multiple PnR runs in parallel. • Proficiency with tools such as Innovus, ICV, and ICC2/FC.
Requirements
- ▸4nm nodes
- ▸floorplanning
- ▸cts-hts
- ▸em/ir
- ▸tape-out
- ▸innovus
Work Environment
Onsite