Principal Engineer - FPGA/ASIC Design

About the Role

In this technical position you will design, verify, integrate, and test FPGA and ASIC solutions for current and future engine control system products. Responsibilities include developing architectures, writing RTL code, running simulations, performing synthesis, creating test benches, and preparing documentation for certification authorities such as DO‑254. • Participate in all project phases, producing design documents, verification plans, and reports. • Design and develop custom ASIC or FPGA devices for engine control units. • Verify complex FPGA/ASIC products to DO‑254 standards. • Write RTL in VHDL/Verilog/SystemVerilog and debug using simulation tools. • Achieve timing closure and generate test benches for FPGA designs. • Evaluate and optimize synthesis, place‑and‑route, timing constraints, and power utilization. • Validate FPGA hardware with oscilloscopes, logic analyzers, ILA, and JTAG.

Key Responsibilities

• ▸asic design
• ▸fpga design
• ▸rtl coding
• ▸timing closure
• ▸synthesis optimization
• ▸hardware validation

What You Bring

Rolls‑Royce is seeking a Principal Engineer – FPGA/ASIC Design Specialist to join its Indianapolis or West Lafayette team. The role operates on a hybrid schedule, allowing a mix of remote and on‑site work, with up to 25% travel between the two locations as needed. The ideal candidate holds a Bachelor’s (5+ years), Master’s (3+ years), or PhD in Electronics or Computer Engineering and must be a U.S. citizen. Preferred experience includes lab validation of FPGA hardware, scripting in TCL/Python/Shell, proficiency with Windows and Linux development, version‑control tools, Actel and Xilinx flows, and model‑based design using MATLAB/Simulink or SysML tools. • Bachelor’s (5+ yr) or Master’s (3+ yr) or PhD in Electronics/Computer Engineering; U.S. citizen. • Proficiency in TCL, Python, or shell scripting. • Familiarity with Windows and Linux development environments. • Experience with version‑control systems such as Git or SVN. • Knowledge of Actel & Xilinx tool flows and model‑based design (MATLAB/Simulink, Cameo SysML).

Requirements

• ▸electronics eng
• ▸python
• ▸linux
• ▸git
• ▸xilinx
• ▸matlab

Benefits

Compensation features a salary range of $113,179‑$183,916 annually, a discretionary bonus, and a comprehensive total rewards package that includes health, dental, vision, retirement savings with company match, paid time off, parental leave, tuition reimbursement, and relocation assistance. Hybrid work flexibility and a supportive workplace culture round out the employee experience. • Competitive salary $113k‑$184k plus discretionary bonus. • Hybrid work schedule (average three on‑site days per week) with remote flexibility. • Relocation assistance and comprehensive benefits including health, dental, vision, 401(k) match, PTO, parental leave, tuition reimbursement, and long‑term incentive plan.

Work Environment

Hybrid